In UVM, a structured mechanism called UVM phases is used to automate the execution of various components within a testbench. This ensures that the simulation follows a defined sequence, streamlining the process. UVM defines twelve key phases, each with a specific role in the testbench lifecycle. The order of execution for these phases is depicted in Figure 1 below.
Figure 1: UVM Phases
The phases can be caterogised as time consumed phases and non-time consumed phase.*Timed phases* are those that involve consuming simulation time, such as stimulus generation or checking, and are implemented as tasks. On the other hand, non-timed phases do not involve any time consumption, as they perform operations that happen instantaneously in simulation time. These are usually implemented as void functions.
| Timed Phase | Non-Timed Phases |
|---|---|
| Run | Build |
| Connect | |
| End of Elaboration | |
| Start of Simulation | |
| Extract | |
| Check | |
| Report | |
| Final |
The UVM phases are grouped into three main categories. These phases help organize the flow of verification tasks, ensuring everything runs smoothly and in the correct order. They are as follows:
Build Phase: This is the first stage, where the testbench is configured and all its components are constructed. During this phase, the necessary environment, such as agents and drivers, is set up.
Run Phase: This is the phase where the actual simulation occurs. The testcases are executed, and time is spent driving signals, applying stimulus, and monitoring responses.
Clean-up Phase: After the simulation, this phase deals with gathering and reporting the results. Any leftover data or processes are cleaned up, and final reports are generated, providing insights into the verification outcome.
Build Phase
The build phase method does not consume any time. Since it is the first phase among several phases it is executed in zero simulation time.
Build
- Instantiate components and subcomponents.
- Get and set values for the components being built.
- All the components are instantiated.
Connect
- All the components are connected via TLM ports.
End of Elaboration
- Necessary display functions such as UVM topology and other configuration settings are completed.
Run Phase
Start of Simulation
- Intended banners such as topology or configuration information are displayed.
- Initial run-time configuration set.
Run
The run phase is executed after the start of the simulation phase and is used for stimulus generation and checking of the DUT. The run phase is implemented as a task and is executed in-order, in parallel. Figure 2, shows the order of the execution with time. Each stage can be subdivided into pre and post stages to add more flexibility. Figure 1, shows the pre and post stages for all the run phase stages.
Figure 2: UVM Run Phase
1. Reset: Reset for the DUT is generated in this phase.
2. Configure: This phase is used to program the DUT and any memories in the testbench so that is ready for the start of the test case.
3. Main: This phase is responsible for generating the stimulus and applying it to the DUT. At the end of this phase, all the test cases are completed.
4. Shutdown: This phase ensures the effects of stimulus generated during the phase have propagated through the DUT.
Clean Up Phase
The clean up phases are used to extract information from scoreboards and functional coverage monitors to determine whether the test case has passed or reached its coverage goals.
Extract
- Simulation time will no longer advance.
- Extracts information from the scoreboards and functional coverage monitors to determine whether the test case is passed or failed.
Check
- Analysis of the components to check that the DUT behaved correctly and identify any errors that may have occurred during the simulation process.
Report
- Report the test results and write the results to a log file if necessary.
Final
- End of verification process.