UVM stands for Universal Verification Method developed by UVM Working Group that provides a standardized methodology for verifying digital integrated circuits. UVM is built on top of SystemVerilog and provides a useful framework for creating reusable and scalable testbenchs. The framework provides a set of building blocks or pre-built design kits that help to create a complex system in a more organized and efficient way instead of building everything from scratch. The verification method uses a factory method to create an object instead of using a direct constructor call to create an object. This method allows the code to instantiate a specific class at runtime. This directory contains examples specifically focused on UVM verification design.
Automated Work Flow
UVM Basics
- UVM Testbench Overview
- UVM Base Class Library
- UVM Report Object
- UVM Common Operations
- UVM Phases
- UVM Resource and Configuration Database
Transaction-Level Modeling (TLM)
- TLM Overview