Source – SV Verification Directory
As the name implies, the solve-before
constraint ensures that the specified constraint is resolved prior to any other constraints during randomization. This feature becomes particularly useful when you need to control the order of constraint solving to achieve specific results or meet dependencies within the randomization process for varible ordering
In a typical scenario, the constraint solver assigns equal priority to all constraints, meaning that the order in which constraints are resolved is non-deterministic. However, when you require certain variables to be solved in a specific order, the solve-before
constraint gives you finer control by changing the probability of occurrences.This allows you to enforce ordering among variables and manage dependencies effectively, especially in complex verification environments where variable relationships influence the final randomized results.
Syntax
constraint <constraint_name> {solve A before B;}
Note
: The randc
variables are always solved before any other constraints. Therefore, variables cannot be declared as randc
when using the solve-before
constraint.
Example code
- From the book SystemVerilog for Verification.
class const_ex;
rand bit x;
rand bit [1:0] y;
constraint const_1 {
solve x before y;
//solve y before x; // do not apply both solve-before constraint at the same time
(x == 0) -> (y == 0);
}
function void disp();
$display("x = %d, y = %d", x, y);
endfunction // disp
endclass // const_ex
module tb_const_solve_before;
const_ex sb;
initial begin
sb = new();
for(int i = 0; i < 16; i++) begin
sb.randomize();
sb.disp();
end
end
endmodule