SystemVerilog – SV Vivado Script – SV Python Script

SystemVerilog was introduced to simplify the verification process by incorporating software features like Object-Oriented Programming (OOP). It significantly enhances testbench development, making the verification of complex designs more manageable. For those looking to experiment with different tools, EDA Playground offers a convenient platform to perform verification using a variety of commercial simulators, such as Cadence Xcelium, Synopsys VCS, and Aldec Riviera-PRO.

In my own workflow, I prefer using Vivado Simulator, as it integrates seamlessly with my design flow. Vivado installation guide can be found here.

Restricted Language Support
Although the Vivado simulator integrates seamlessly with my design flow, it lacks support for certain SystemVerilog attributes. As a result, I transitioned to the QuestaSim Starter version. However, the starter version of QuestaSim has limited support for SystemVerilog, particularly for advanced verification features. This ultimately led me to fully transition to EDA Playground which has become my go-to platform for developing and experimenting with verification environments.

Project Folder

The main directory is named Projects and is located in the home directory. Within this, there are two key subfolders:

  1. FPGA_Projects: This folder contains all the FPGA-related projects.
  2. Python_Scripts: This folder holds Python scripts related to the FPGA projects.

This structure keeps projects and supporting scripts well-organized for efficient workflow management. The folder structure I use is outlined below:

Projects
.
├── FPGA_Projects
│   ├── SystemVerilog_Verification
│   │   ├── Readme.org
│   │   ├── sv_tcl_script
│   │   └── sv_verification
│   ├── UVM
│   │   ├── uvm_tcl_script
│   │   ├── uvm_templates
│   │   └── uvm_verification
│   ├── VanillaFPRO
│   │   ├── Design_Tests
│   │   ├── Drivers
│   │   ├── HDL
│   │   ├── Projects
│   │   └── ZyboZ7_BoardFiles
│   ├── ZyboZ7
│   │   ├── BoardFiles
│   └── iVerilog
│       ├── README.org
│       ├── design
│       ├── doc
│       └── tb_design
│
└── Python_Scripts
    ├── iVerilog
    ├── sv_scripts
    ├── uvm_scripts
    └── vivado

Note: To run the Python scripts from any directory in your terminal, you’ll need to add the folder/file path to your .zshrc or .bashrc file. This ensures the scripts are accessible globally, regardless of your current working directory.

Verification Folder Structure

The SystemVerilog_Verification repository on GitHub is structured into two key sections:

  1. sv_tcl_script: This folder contains a Tcl script designed to automate the simulation process in Vivado, making it easier to run and manage simulations efficiently.
  2. sv_verification: This folder includes a collection of verification designs, providing a comprehensive set of examples for verifying SystemVerilog code.
SystemVerilog_Verification
.
├── sv_tcl_script
|   └── sv_run.tcl
└── sv_verification
    ├── associative_arrays
        └── tb_associative_arrays.sv
    .
    .
    .

Python Script

A Python script, sv_design.py, is designed to automate the creation of a project folder within the sv_verification directory. When executed, it generates the necessary SystemVerilog (SV) verification files, with the top-level testbench file labeled as tb_<design_name>.sv.

To simulate the design, the sv_run.py script is used, which calls the Vivado simulator. This script, in turn, invokes the sv_run.tcl file located in the sv_tcl_script folder. The project folder will be named verif within the design directory.

Additionally, the sv_clean.py script is available to remove the project folder and clean up Vivado log files, ensuring a tidy workspace.

sv_design.py <design_name>    // create the design
sv_run.py    <design_name>    // execute the simulation
sv_clean.py                   // removes the project and log files created by Vivado

Steps to Create and Simulate a SV Verification Project

  • Open your terminal and create the design environment by executing the sv_design.py script. For example, to create a verification project named “test”, run the following command:
sv_design.py test

  • A folder named test will be generated inside the sv_verification directory, and the top-level file will be named tb_test.sv.

  • Complete the necessary design files, then execute the sv_run.py script to begin the simulation. For example:

sv_run.py test
  • This will create a project folder named verif inside sv_verification/test and display the simulation results in the terminal.