SV Verification Directory

Clocking Block

Clocking block in a testbench is implemented to manage timing relationship and synchronization for a group signals. t provides a clear and organized way to define the clocking events, control the sampling and driving of signals, and synchronize operation.

  • Groups signals under a common clock, specifying how and when signals are sampeld and driven with respect the clock.
  • Provide specification to model clock skew for input and output.

Input and Output Skew

Idealy, clock skew refers to the variation in arrival times of a clock signal at different components within a system. In SystemVerilog, clock skew can be modeled by specifying an integer value before the signal name within a clocking block. Figure 1 illustrates the specification of input and output skew in SystemVerilog testbenches.

  • Input Skew: The input data is sampled after a specified duration from the clock edge.
  • Output Skew: The output data is driven after a specified duration from the clock edge.
Figure 1: Input and Output Skew

Figure 1: Input and Output Skew

Syntax

clocking cb @(posedge clk);
   input  #2ns data_in;     // sample data in 2ns after the clock edge
   output #4ns data_out;    // drive  data 4ns after the clock edge
endclocking