Interface
Interface in SystemVerilog is a construct that bundles all the signals together or group related to signals so that they can be shared among multiple modules in the verification environment. This simplifies the connection between modules, improves code readability, and reduces the likelihood of errors in complex designs.
Syntax
// create interface
interface interface_name;
signals;
endinterface
// intantiate interface in a module
inteface_name inst_name;
Example Code
Design
module add ( // outputs s, // inputs a, b ); // outputs output [4:0] s; // inputs input [3:0] a, b; assign s = a + b; endmodule
Testbench
interface intf; logic [3:0] a; logic [3:0] b; logic [4:0] s; endinterface module test; intf i_intf(); add DUT(.a(i_intf.a), .b(i_intf.b), .s(i_intf.s)); initial begin $display("---------- ADDER ----------"); repeat(10) begin i_intf.a = $random(); i_intf.b = $random(); #1; $display("a = %d, b = %d => s = %d", i_intf.a, i_intf.b, i_intf.s); end end endmodule
Advantages
- Addition and deletion od signals are easy since all the signals are at one place.
- The signals can be grouped and passed as a signal port rather than multiple port declaration.
- Signals can be grouped based on direction (Modport) and timing information (Clocking Block).
Virtual Interface
- Both the interface and module are static, meaning they exist throughout the simulation and are straightforward to connect.
- Since both are static, connecting them is as simple as wiring them together.
- Unlike interfaces, classes are dynamic—they are instantiated only when needed.
- Interfaces, being static, cannot be directly used inside a class since the two follow different lifecycles.
- To access an interface from within a class, the
virtual
keyword must be used during instantiation. - A virtual interface provides a handle to the static interface, allowing it to be used within a class-based environment.
- One advantage of a virtual interface is that it can be assigned dynamically at runtime, providing flexibility.
- A virtual interface must be initialized (assigned to a valid interface instance) before it can be accessed or driven. Failure to do so will result in errors during simulation.