Source – SV Verification Directory

Inheritance

Inheritance allows a new class to inherit properties and methods from an existing class.

  • Creates an extended class from an existing class.
  • The existing class is called as base class or parent class and the extended class is called as the derived class or the child class.
  • The extends keyword is used to inherit the properties of the parent class to the child class.
  • Multilevel inheritance is possible in SystemVerilog i.e., a child class can be extended again which inturn can be extended.

Advantages

  • Code reusablity.
  • Provides over riding of parent class from the child class.
  • Improves modularity of the code.

Note: to overide the parent class properties and methods, the child class should have the same name for class properties and methods. To access the parent class method or properties use Super Keyword or create a handle for parent class.

Example Code

// Parent class
class parent_class;
   // class properties or variables
  int a, b, s;

   // task method
  task sum (int a,b);
    s = a + b;
    $display("a = %0d , b = %0d, sum s = %0d", a, b ,s);
  endtask

endclass

// Child Class
class child_class extends parent_class;
  // class properties or variables
  int m;

  // task method
  task mul (int a,b);
    m = a * b;
    $display("a = %0d , b = %0d, mul m = %0d", a, b ,m);
  endtask

endclass

// Multilevel Inheritance
class gran_child_class extends child_class;
  // class properties or variables
  int d;

  // task method
  task div (int a,b);
    d = a / b;
    $display("a = %0d , b = %0d, div d = %0d", a, b ,d);
  endtask

endclass


module tb_inheritance;

  gran_child_class cl_obj;      // declare a class handle of type cl_obj

   initial begin
     cl_obj = new( );      // construct an object
     cl_obj.sum(30,10);    // access a method
     cl_obj.mul(30,10);    // access a method
     cl_obj.div(30,10);    // access a method
   end

endmodule

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