Source – SV Verification Directory

Object

An object is an instance of a class. It is similar to the instantiation of a module in Verilog, but there are some differences which as listed in the table below:

Verilog Module InstanceSystemVerilog Class Instance
A module is instantiated during compile timeA class is instantiated during simulation when needed by the testbench
Verilog instances are static, as hardware does not change during simulationClass objects are created when required and freed from memory when no longer needed

The ’new’ keyword is used to instantiate the object.

class Ex_class;
   // class properties or variables
  int a, b, s;

   // task method
  task sum (int a,b);
    s = a + b;
    $display("a = %0d , b = %0d, sum s = %0d", a, b ,s);
  endtask

endclass


module test;

  Ex_class cl_obj;      // declare a class handle of type cl_obj

   initial begin
     cl_obj = new( );   // construct an object
     cl_obj.sum(30,10); // access a method
     repeat(10)
        cl_obj.sum($urandom_range(1,50),$urandom_range(1,50));
   end

endmodule

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Points to Remember

  1. Objects are created dynamically using ’new’ keyword.
  2. Properties (variables) of an object can be accessed using a handle.
  3. Objects are allocated on the heap, and their lifetime is managed by the simulation runtime.
  4. Objects from one class can communicate with objects in another class, efficient in managing different verification environments.
  5. If an object is not created, then the default value for the class handle is null.
  6. A handle can only point to objects of one type, hence, they are called “type-safe”.