Tasks

Source – SV Verification Directory

Tasks

Task in SystemVerilog is a procedural block that contains a block of code that can be reused. Unlike [Functions], tasks can contain simulation time. The default port direction is “input” unless declared as other types. The default data type of the ports is of “logic” type unless specified. A task does not need to have a “begin … end” statement.

Syntax

task task_name (in1, in2, in3, output logic out1);
   // execute the code
endtask

Example Code: Task

module task_ex;

  logic [3:0] data;
  logic [3:0] arry[16];

  task incr([3:0] in, output logic [3:0] out);
    out = in + 1;
  endtask

  initial begin
    data = 0;
    $display("--------- Task: Increment ---------");
    //$display("data = %0d", data);
    arry[0]= data;
    for(int i=0; i<15; i++)begin
      incr(arry[i], arry[i+1]);
      $display("data = %0d", arry[i+1]);
      #1;
    end
  end

endmodule

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Static Task

When the task is declared as static, all its variables are stored in the same storage space for all the task calls. This means that if a static task is called multiple times, the same variables are used, which can lead to unintended interactions if not managed carefully. Static tasks are useful when the state needs to be maintained across multiple invocations.

Example Code: Static Task

module static_task;

  logic [3:0] data = 0;
  logic [3:0] arry[16];

  task incr;
    data++;
  endtask

  initial begin
    $display("--------- Task: Increment ---------");
    for(int i=0; i<15; i++)begin
      incr();
      $display("data = %0d", data);
      #1;
    end
  end

endmodule

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Automatic Task

Automatic task allocates separate memory for each call in the stack. This is useful for tasks that may be called recursively, as it prevents variable conflicts and unintended interactions between different calls. An automatic task can be declared with an “automatic” prefix to the task name.

Example Code: Automatic Task

module auto_task;

  logic [3:0] a,b;
  logic [4:0] res;

  task automatic sum([3:0] a, b, output logic [4:0] sum);
    sum = a + b;
  endtask

  initial begin
    $display("----------- Automatic Task: Addition -----------");
    repeat(30)begin
      a = $urandom();
      b = $urandom();
      sum(a,b,res);
      $display("a = %0d, b = %0d, sum = %0d", a, b, res);
    end
  end

endmodule

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Points to Remember

• Automatic variables can be declared in a static task.
• Static variables can be declared in an automatic task.
• Default argument type is logic if no type is specified.
• The default direction of the argument is input if no direction is specified.