Break and Continue

SV Verification Directory

Break and Continue

Break and continue in SytemVerilog is used to control the loops. When a “break” statement is encounted, the loop is terminated and control moves to outside of the loop. Whereas, when a “continue” statement is encounted, the consecutive blocks of code is skipped and the control is moved to the next loop iteration value.

Example Code: Break and Continue

module break_and_continue;

  initial begin
    int i = 0;
    $display("---------- Even Number ----------");
    forever begin
      if(i % 2 == 0) begin
        $display("%0d is an Even Number", i);
        i = i + 1;
        continue;
      end else begin
        if(i > 20)
          break;
      end
      i = i + 1;
      #1;
    end
  end

endmodule

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