Source – SV Verification Directory
Repeat and Forever Loops
The “repeat” and “forever” loops are another looping constructs available constructs in SystemVerilog, to execute a loop of code for a specific number of times or indefinitely. These loops are especially useful in testbenches and design verification when you need controlled or infinite iterations.
Repeat
The repeat loop executes a block of code a specified number of times. This loop is handy when you know the exact number of iterations required.
Syntax
repeat (count) begin
// execute the code
end
Example Code
module tb_repeat_code;
initial begin
int i = 0;
$display("---------- 3 times table ----------");
repeat(11)begin
$display("3 x %0d = %0d", i, i*3);
i = i + 1;
end
end
endmodule
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Forever Loop
The “forever” loop executes a block of code indefinitely until it is interrupted by a disable statement, a break statement, or some external condition like a simulation time limit.
Syntax
forever begin
// execute the code
end
Example Code
module tb_forever_code;
initial begin
int i = 0;
$display("---------- 3 times table ----------");
forever begin
i = i + 1;
#1;
$display("3 x %0d = %0d", i, i*3);
if(i==10)
break;
end
end
endmodule