Structure
One of the biggest limitations of Verilog is the lack of data structures. In SystemVerilog, you can create a structure using the struct statement. A structure is a collection of data that can be synthesized.
Example of struct:
struct {logic [7:0] data_a, data_b, data_c;} data_s;
data_s in_data;
NOTE: By default a structure is unpacked.
Typedef for Struct
To create multiple structure variables it is necessary to use typedef data type.
Packed Structure
A structure is declared as packed with the packed keyword. Packed structures are used when the underlying bits represent a numerical value to when you are trying to reduce memory usage.
Example of declaring packed structure:
type struct packed {logic [&;0] data_a, data_b, data_c} data_s;
data_s in_data;
Choosing Between Packed and Unpacked Structure
Packed
- If you plan on making aggregated operations on the structure, such as copying the entire structure, a packed structure is more efficient.
Unpacked
- If your code accesses the individual members more than the entire structure use an unpacked structure.
Reading and writing elements with odd sizes in a packed structure requires expensive shift and mask operations.