Source – SV Verification Directory
Enumeration
In Verilog, it is possible to declare user-defined types using a define macro, shown below:
`define TYPE1 8
`define TYPE2 32
This does not create a new type but just performance text substitution. In SystemVerilog, a new type can be created with the following code:
typedef logic [Size-1:0] VAR_T;
VAR_T var1, var2;
The typedef and parameter statements can be put in a package so they can be shared across the design and testbench. A good use for a user-defined type is an associative array, which must be declared with an index.
Enum Data Type
An enum data type defines a set of named values. The enumerated type declaration contains a list of constant names and one or more variables.
Example of a enum data type is shown below:
enum {apple, banana, peach, orange} fruits_t;
fruits_t fruit;
Combining typedef with enum allows the user to define easily readable data types.
Example of enumeration in SystemVerilog is given below:
module type_enum ();
typedef enum {apple, banana, peach, orange, berry} fruits_t;
fruits_t fruits;
initial begin
//fruits.first();
$display("-------------- Enumeration --------------");
for(int i = 0; i < fruits.num(); i++)begin
$display(" \t fruits[%0d] = %0s", fruits , fruits.name);
fruits = fruits.next();
end
end
endmodule