Logic Type
Data Types
SystemVerilog includes all the data types that are available with Verilog and add many new data types to help both hardware design engineers and verification engineers. Below is a table showing an extensive list of data types availabe in SystemVerilog.
| Language | Data Type | State Type | No. of Bits | Signed/Unsigned | C Equivalent |
|---|---|---|---|---|---|
| SystemVerilog/Verilog | Wire | 4 | >=1 | Unsigned | - |
| SystemVerilog/Verilog | Reg | 4 | >=1 | Unsigned | - |
| SystemVerilog/Verilog | Interger | 4 | 32 | Signed | - |
| SystemVerilog/Verilog | Real | 2 | Double Precision Floating point | Double | |
| SystemVerilog/Verilog | Time | 4 | 64 | Unsigned | - |
| SystemVerilog | Logic | 4 | >=1 | unsigned | - |
| SystemVerilog | Bit | 2 | >=1 | unsigned | - |
| SystemVerilog | Byte | 2 | 8 | Signed | Char |
| SystemVerilog | Int | 2 | 32 | Signed | Int |
| SystemVerilog | Shortint | 2 | 16 | Signed | Short Int |
| SystemVerilog | Longint | 2 | 64 | Signed | Long Int |
Note: signed variables can cause unexpected results with randomization.
2-State and 4-State Data Type
In verilog the data types is differntiate based on the way they are assigned and store values. NET is a variable that connects two structural entities, these varibale do not store an values and their sole purpose is to pass the driving value from the driver circuit forward. Some net data types are wire, tri, wor, trior, wand, triand, tri0, tri1, supply0, supply1 and trireg. WIRE is the more frequently used data type. Unlike NET, REGISTER variable store a value and they are used in procedural blocks. Some register data types are: reg, integer, time and real. Reg is the most frequently used type. Reg is used for describing logic, integer for loop variables and calculations, real in system modules, and time and real-time for storing simulation times in test benches.
These verilog data type can hold four values as described in the table below:
| Value | Definition |
|---|---|
| 0 | Logic 0 or False |
| 1 | Logic 1 or True |
| X | Unknow Value |
| Z | High Impedence of Tristate Gate |
- 4-State Data Type: can hold all the 4 values mentioned in the above table.
- 2-State Data Type: can hold only 0 or 1 value.
Logic Type
In Verilog is important to declare a varible as wire or reg before writing the logic to use them. Sometime when the logic written is changed it is important to change the variable type also. SystemVerilog erradicates this step with the inclusion of logic data type. A logic signal can be used anywhere a net is used, except when modelling a bidirectional bus, and when using a register data type. One advantage of logic data is when it produces as error when a net type is driven by multiple ports unless desired. You can use the logic type to find netlist bugs as this type can only have a single driver.