SV Verification Directory

In the rapidly evolving world of digital design, verification is paramount to ensuring that designs function correctly and efficiently. SystemVerilog, an extension of the Verilog hardware description language, has become a critical tool for verification engineers. This blog post aims to introduce SystemVerilog verification, highlighting its significance, features, and basic concepts to help you get started on your verification journey.

Automated Workflow in Vivado

• SV Verification Workflow in Vivado

Layered Testbench

• SV Testbench Overview

Data Types

• Logic Type
• Fixed-Size Arrays
• Packed and Unpacked Array
• Dynamic Arrays
• Queues
• Associative Arrays
• Array Methods
• Enumeration
• Structures
• Streaming Operator

Type Converstion

• Static Cast
• Dynamic Cast

Flow Control

• For and Foreach Loops
• While and Do While Loops
• Repeat and Forever
• Break and Continue

Tasks and Functions

• Tasks
• Functions

Process

• Fork Join
• Fork Join Any
• Fork Join None
• Wait Fork
• Disable Fork

OOP in SV

• Object-Oriented Programming
• Class
• Handle
• Object
• Method
• This Keyword
• Static Class Properties and Methods
• Shallow Copy and Deep Copy
• Four Pillars of OOP
• Inheritance
• Super Keyword
• Virtual Keyword
• Polymorphism
• Encapsulation

Interprocess Communication

• Events
• Mailbox
• Semaphore

Interface

• Interface
• Modport
• Clocking Block

Randomization

• $urandom and $urandom_range
• rand and randc
• Constraint Randomization
• Constraint: Inside Operator
• Constraint: Array Randomization
• Constraint: Bidirectional and Conditional
• Constraint: Implication and Equivalence
• Constraint: Solve-Before
• Constraint: Weighted Distribution
• Constraint: In-line and External

SV Mastery Challenges

• Constraint Challenges

Verification Examples

• Half Adder
• Full Adder
• Adder Subtractor