Latch and Flip-Flop

Source – RTL Design Directory

Latchs and Flip-Flops are fundamental digital components used to store information. Both play a critical role in sequential circuits, but they differ in their operation and applications.

Latch

A latch is level-sensitive memory element that stores a single bit of data. It operates based on the state of an enable signal:

• Transparent Mode: When the enable signal is active, the latch allows data to flow through, making it “transparent.”
• Hold Mode: When the enable signal is inactive, the latch retains its last state, effectively “latching” the data.

Latches are commonly used in designs where immediate data storage or asynchronous operation is required.

always@(en, rst, in)begin
   if(rst)
     l_out <= 1'b0;
   else
     if(en)
        l_out <= in;
end

The figure below shows the waveform of a latch. When the enable signal is high, the output is directly connected to the input, regardless of the clock. In this case, the clock is included simply to demonstrate that the output does not depend on it. This behavior makes the latch asynchronous, as the output changes immediately in response to the input when the enable signal is active, without waiting for a clock edge.

Flip-Flop

A flip-flop is a edge sensitive memory element that stores a single bit of data. It operates based on edges of the clock signal. A flip-flop is combining two latches in a master-slave configuration.

• Positive Edge Trigger: The data is captured on the rising edge (from low to high) of the clock signal and will hold the data until the next rising edge.
• Negative Edge Trigger: The data is captured on the falling edge (from high to low) of the clock signal and will hold the data until the next falling edge.

// rising edge
always@(posedge clk)begin
   if(rst)
        d_r_out <= 1'b0;
   else
        if(en)
          d_r_out <= in;
end

// falling edge
always@(negedge clk)begin
   if(rst)
        d_f_out <= 1'b0;
   else
        if(en)
          d_f_out <= in;
end

The waveform below illustrates the operation of a D flip-flop. The output of the flip-flop only changes on the rising or falling edge of the clock signal. Once the output is updated, it is held constant until the next change in the clock edge, ensuring stable storage of data between clock transitions.

Applications

• Latches: Used in asynchronous circuits, temporary data storage, or as part of larger flip-flop designs which will be decribed in the subsequent section.
• Flip-Flops: Widely used in registers, counters, and synchronous sequential circuits where precise timing is essential.