Source – RTL Design Directory

In Verilog, == and === are both used for comparison, but they behave differently in how they handle X (unknown).

== Equality

The == operator checks if two values are logically equal. It used for comparisons on only 1’s and 0’s. If any operand contains an X, the comparison result will be a unknown value.

Example:

4'b101X == 4'b1011;  // Result: x (unknown)
4'b1X00 == 4'b1100;  // Result: x (unknown)

=== Equality

The === operator is a strict equality check. It treats X as don’t-care values. When both RHS and LHS are X’s the results will true (high).

Example:

4'b101X === 4'b101x;  // Result: true
4'bxxxx === 4'bxxxx;  // Result: true

Here, === treats X as a distinct value, so the comparison returns false if the two values are not strictly equal, including the X bits.

NOTE: In synthesizable RTL, it is not advisible to use === since it will hide “X” propogations issues.

Points to Remember

  1. == : Ignores X and checks for logical equality.
  2. === : Considers X in the comparison and checks for strict equality. It is not considered for synthesizable RTL.