Clock Gating

Clock gating is a widely used technique to reduce dynamic power consumption in digital circuits, particularly in complex systems like processors and FPGAs. Before diving into the benefits of clock gating, let’s take a look at the following SystemVerilog code snippet:

always_ff@(posedge clk)
   if(en)
     Dout <= Din;

The gate-level diagram of this code is illustrated in Figure 1. In this design, a multiplexer (MUX) controls the data flow, ensuring that when the ‘En’ signal is high, ‘Din’ is passed to ‘Dout’ on the next clock edge. However, this MUX can be replaced with an AND gate to describe the conditional effect more efficiently.

In the design above, the flip-flop always receives the clock signal, leading to unnecessary power consumption even when the output ‘Dout’ is not changing (i.e., when ‘En’ is low). This continuous clock supply results in dynamic power loss, which can be significant, especially in large-scale designs.

When ‘En’ is high, the flip-flop captures the ‘Din’ value and updates ‘Dout’ accordingly. When ‘En’ is low, ‘Dout’ remains unchanged. However, the flip-flop still receives the clock signal, toggling its internal circuitry and consuming power. Ideally, when the output is not required, it’s more efficient to disable the flip-flop by stopping the clock, thus saving power.

Incorporating clock gating in designs can significantly reduce dynamic power consumption, making it an essential technique in power-efficient digital systems.

And Based Clock Gating

Clock gating tackles power consumption issue by adding logic to control the clock signal itself. When ‘En’ is low, the clock to the flip-flop is gated (turned off), preventing unnecessary toggling and reducing power consumption. This gating mechanism can be implemented using an AND gate to control the clock signal based on the ‘En’ condition.

Figure 2: And Based Clock Gating

At first glance, the design might seem straightforward, but it comes with its own set of challenges. One key issue is its susceptibility to glitches, as can be seen in the waveform.

Figure 3: Glitches in Gated Clock

When examining the waveform, it can be noticed that an unexpected transitions, or “glitches,” can occur. These glitches are typically caused by slight delays in the signal propagation, which can result in incorrect values being latched by the flip-flops. Even a simple design can face issues like these, especially when dealing with high-speed or asynchronous signals.

Addressing these glitches requires careful consideration of the circuit’s timing and synchronization, making the design more complex than it initially appears.

Latch Based Clock Gating

While an AND gate can be used for simple clock gating, this approach is prone to glitches due to the direct application of the enable signal ‘En’. To address this, a latch-based clock gating design is often implemented.

In this improved design, the enable signal En is first passed through a latch before being applied to the AND gate for clock gating. The latch helps synchronize the En signal, ensuring it changes state only when the clock is stable. This effectively eliminates glitches that can occur in the basic AND-gate-based clock gating design. This is a prime example of when using a latch is beneficial.

Figure 4: Latch Based Clock Gating

In the waveform shown below, it can be seen how the use of a latch helps manage glitches on the enable signal ‘En’. Even if a glitch occurs on ‘En’, the negative edge-sensitive latch effectively “smoothens” it, ensuring that only stable transitions are passed through.

The output of this latch is then combined with the clock signal using an AND gate to produce a glitch-free gated clock. By allowing only clean transitions from the enable signal, this approach ensures that the gated clock is stable and reliable, preventing unintended toggling in the flip-flops. This is a key benefit of using latch-based clock gating over simple AND-gate designs.

Figure 5: Clock Gating

The code snippet below demonstrates how to implement a glitch-free gated clock using a latch.

always_comb
  if(!CLK)
    Latch_En <= En;

assign G_CLK = Latch_En & CLK;

Effects of Clock Gating

Pros

Reduced Dynamic Power Consumption: By disabling the clock for inactive modules, clock gating significantly reduces power usage, making the system more efficient.
Lower Heat Dissipation and Enhanced battery life: With less power consumed, there is a corresponding decrease in heat generation, and reducing power consumption directly extends battery life helping to maintain the device’s thermal performance.

Cons

Timing Violations: When additional logic, such as AND gates or latches, is introduced into the clock path, it can delay the clock signal, leading to setup or hold time violations.
Clock Skew: When using clock gating, the distribution of the gated clock can introduce skew between different parts of the circuit, affecting clock synchronization.

Clock Gating#

And Based Clock Gating#

Latch Based Clock Gating#

Effects of Clock Gating#

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