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Full Case and Parallel Case

The case statement is a fundamental construct used for conditional branching across various programming languages. In SystemVerilog, it is implemented as a simple if-else-if statement. SystemVerilog introduces two specialized variations of the case statement, casex and casez, that allow for handling “don’t care” conditions in the case items, discussed in Casex and Casez.

The case statement can be caterogired as full and parallel based on the how the case items are being matched to case expression.

Full Case

A full case statement is where every possible value of the case expression is matched to a case item or to a default case statement. Not having a default statement will not result in a full case statement. When the case item does not have a matching case expression the output will hold the last assigned value and the synthesis will infer a latch.

From an HDL simulation perspective, a “full” case statement is a case statement in which every possible binary, non-binary and mixture of binary and non-binary patterns is included as a case item in the case statement [1].

From a synthesis tool perspective, a “full” case statement is a case statement in which every possible binary pattern is included as a case item in the case statement [1].

  • Full Case removes latches from the design.
  • Number of case item is directly proportional to the number of case expression.
  • The full_case directive can be used to explicitly indicate that the case statement is full.

Parallel Case

A case statement checks the case expression against multiple cases and executes the corresponding branch that matches the case expression. By default, the synthesis tools generate a priority encoder, which checks cases sequentially. The parallel case tells the synthesis tool that each case item has only one matching case expression allowing the synthesis tool to optimize the hardware by removing priority checks, leading to simpler and faster hardware implementation.

  • Parallel Case removes large, slow-priority encoders.
  • The parallel_case directive is used to explicitly indicate that the case statement is parallel.

Points to Remember

  1. Non-Parallel Case: The order of the case branches is significant, as the conditions are evaluated sequentially, and the first matching condition is selected for execution.

  2. Parallel Case: The order of the case branches is irrelevant, as the synthesis tool assumes that the conditions are mutually exclusive, allowing for simultaneous evaluation without prioritization.

Reference

  1. “full_case parallel_case”, the Evil Twins of Verilog Synthesis
  2. Cummings, Clifford. “SystemVerilog’s priority & Unique–A Solution to Verilog’s full_case & parallel_case Evil Twins.” SNUG. Israel 282282 (2005).