Synchronous and Asynchronous Reset

Resets are crucial in digital circuits for ensuring the system starts from a known state.

Resets allow the system to recover from errors by reinitializing the state.
Resets ensure that all flip-flops start from a known state.

There are two types of resets based on the reset activation and they are:

Synchronous Reset
Asynchronous Reset

Synchronous Reset

In synchronous reset circuits, the reset signal is synchronized with the clock. When the reset is applied, the action only occurs at clock edges (positive or negative edge), avoiding glitches and metastability. The coding style to model synchronous reset is an if/else priority style with reset in the if condition and all the other logic in the else section. This type of logic will be implemented as shown in the figure below:

The input signal is ANDED with the reset signal before reaching the register. In some implementations, a MUX will be implemented in place of an AND where the reset is the select input, one of the inputs is tied to the ground, and the other to set to the input.

Example

module syn_rst(clk, rst, d, q);
  // outputs
   output q;
   // inputs
   input d;
   input clk;
   input rst;

always_ff@(posedge clk)
  if(!rst)
    q <= 1'b0;
  else
    q <= d;

endmodule

Advantages

Synchronous reset ensures the entire circuit is synchronous all the time.
Synchronous resert ensures the reset actions occur at the clock edges, preventing the flip-flop from going into metastability.
When the reset is generated by an internal condition, synchronous resets are advisable to be implemented as they filter out any glitches.
Working

Disadvantages

The reset signal should be applied long enough so that the clock edge samples the reset signal.
A pulse stretcher should be implemented to stretch the reset signal to guarantee to sample the reset signal.
Synchronous reset require a clock to reset the circuit.

Asynchronous Reset

Asynchronous reset does not depend on the clock and its effect is seen immediately as the reset is applied. Asynchronous reset flip-flop incorporates a reset pin. The reset pin is typically active low, the flip-flop goes into the reset state when the reset signal goes to a logic low (0). The figure below shows the implementation of an asynchronous reset flip-flop with a reset pin.

From the figure it can be seen that additional logic is not required with the input to the flip-flop. To code an asynchoronous reset in Verilog, the reset signal must be included in the sensitivity list. The reset is given the highest priority in this style of coding.

Example

module syn_rst(clk, rst, d, q);
  // outputs
   output q;
   // inputs
   input d;
   input clk;
   input rst;

always_ff@(posedge clk or negedge rst)
  if(!rst)
    q <= 1'b0;
  else
    q <= d;

endmodule

Advantages

Does not require a clock to reset the circuit.
The data path is guaranteed to be clean if asynchronous reset flip-flops are available.

Disadvantages

Reset assertion is not an issue as the flip-flop takes care of it, but during deassertion when the reset is released close to the active edge of the flip-flop, the flip-flop may go into the metastable stage.
Spurious resets due to noise or glitches on the system reset.

Reset Deassertion

Reset deassertion is the process of bring the system out of reset state to operation state. During asynchronous reset deassertion there are two potential problems

Reset Recovery
- Reset removal time is the minimum time required between the deassertion of the reset signal and the next active clock edge to ensure proper functionality. This concept is similar to setup time in its importance for guaranteeing stable and reliable operation of digital circuits.

Reset Removal
- Reset removal time is the minimum duration for which the reset signal must be deasserted to ensure that flip-flops are correctly initialized.

Verilog has three built-in commands to model and test recovery time and signal removal timing checks: $recovery, $removal and $recrem (the latter is a combination of recovery and removal timing checks)[1,2].

Reset Synchronizer

When an asyn reset is deasserted it should satisfy the timing constraints (reset recovery and reset removal) if not chances are that the system may enter into a metastable state. Therefore, it is necessary to pass the data through [Two-Flop Synchronizer] to avoid metastable conditions. Figure 3 illustrates an approach designed to leverage the advantages of both asynchronous and synchronous reset styles.

Figure 3: Async Reset with Two-Flop Synchnronizer

The second flip-flop in the synchronizer ensures the data is sampled correctly by eliminating any metastability caused by asynchronous reset removal and reset deassertion occurring too close to the active edge of the clock.

Example Code:

module asyn_rst(/*AUTOARG*/
   // Outputs
   rst_main,
   // Inputs
   clk, rst_asyn
   );
  input   clk;
  input   rst_asyn;
  output  rst_main;

  /*AUTOREG*/
  // Beginning of automatic regs (for this module's undeclared outputs)
  reg			rst_main;
  // End of automatics
  /*AUTOWIRE*/

  reg temp_rst;

  always@(posedge clk, negedge rst_asyn)
    begin
        if(!rst_asyn)
                {rst_main, temp_rst} <= 2'b00;
        else
                {rst_main, temp_rst} <= {temp_rst, 1'b1};
    end

endmodule

Note: Reset-glitch filtering circuit must be implemented to ensure a clean reset is received in an asynchronous reset circuits.