Ring Counter: An Overview
A ring counter is a type of shift register that where the output of the last register is fed to the input of the first register forming a type of circular shift register. There are two types of ring counters based on how the last bit is fed to the input and they are:
- Simple Ring Counter
- Twisted Ring Counter
Simple Ring Counter
A simple ring counter is where the output of the last register is fed to the input of the first register. At reset, the initial values of the first register is set to high (‘1’) and the rest to low (‘0’). On every clock cycle, the initial set bit is shifted right. Therefore, the total number of unused states is given by (2**N-N) where N is the input width. For a 4-bit simple ring counter, the input N = 4, the total states are 2**4 = 16 and the total number of unused states is 2**4 - 4 = 12.
Verilog Code: 4-bit Ring counter
module simp_ring_cntr #(parameter N = 4)(/*AUTOARG*/
// Outputs
sr_cntr,
// Inputs
clk, rst
);
// outputs
output [N-1:0] sr_cntr;
// inputs
input clk;
input rst;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [N-1:0] sr_cntr;
// End of automatics
/*AUTOWIRE*/
always_ff@(posedge clk)
if(rst)
sr_cntr <= 1;
else
sr_cntr <= {sr_cntr[0],sr_cntr[N-1:1]};
endmodule // simp_ring_cntr
Twisted Ring Counter
A twisted ring counter is one where the output of the last register is negated and fed to the input of the first register. Unlike in a simple ring counter, on reset, all the registers are cleared or set to zero. Since the inverted output of the last register is fed to the input of the first register, the total number of unused states is given by (2**N-2N) where N is the input width. For a 4-bit twisted ring counter, the input N = 4, the total number of states is 2**4 = 16 and the total number of unused states are 2**4 - 2*4 = 8.
Verilog Code: 4-bit Twister Ring Counter
module twist_ring_cntr #(parameter N = 4) (/*AUTOARG*/
// Outputs
tr_cntr,
// Inputs
clk, rst
);
// outputs
output [N-1:0] tr_cntr;
// input
input clk;
input rst;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [N-1:0] tr_cntr;
// End of automatics
/*AUTOWIRE*/
always_ff@(posedge clk)
if(rst)
tr_cntr <= 0;
else
tr_cntr <={~tr_cntr[0], tr_cntr[N-1:1]};
endmodule // twist_ring_cntr