Encoder

Source – RTL Design Directory

Encoder: An Overview

An encoder is a digital combinational circuit that converts 2^n inputs to n outputs. It converts a set of binary inputs to binary-coded output, where only one input line is active at a given time.

Design: 4-to-2 Encoder

A 4-to-2 encoder, where n = 2 i.e., it consists of 2^n = 2^2 = 4 input lines named as in[3], in[2], in[1], in[0] and two output lines named as out[1] and out[0].

From the truth table, the boolean equation of the 4-to-2 encoder can be written as:

out[0] = in[1] + in[0]

out[1] = in[3] + in[2]

Design: 8-to-3 Encoder

An 8-to-3 encoder consists of eight inputs and three outputs. For the eight-bit inputs, only one of them will be hight at a given time. The truth table for an 8-to-3 encoder is as follows:

The boolean equation for the 8-to-3 encoder can be written as:

out[0] = in[1] + in[3] + in[5] + in[7]

out[1] = in[2] + in[3] + in[6] + in[7]

out[2] = in[4] + in[5] + in[6] + in[7]

Implementing an encoder can be in Verilog achieved with the help of a for loop. It is necessary to abide by certain constraints when implementing a for loop in Verilog. They are as follows:

1. No dynamic looping: Verilog language does not support dynamic looping, i.e., the iteration count should be a constant and should not change during run time.
2. Loop variable: the iteration loop variable e.g. “i” should be declared as an integer.

During simulation and synthesis, the for loop will unroll and be converted into hardware logic.

Verilog Code: 8-to-3 Encoder

always_comb begin
   out = 'h0;

   for(int i = 0; i < 8; i = i+1)begin
      if(in[i])
            out = i;
   end
end