Welcome to my comprehensive collection of RTL(Register Transfer Level) designs. It is an evolving collection highlighting my projects, skills, and achievements in digital circuit design and verification. I specialize in developing efficient, high-performance hardware architectures using industry-standard languages like SystemVerilog and Verilog. Explore my blog for insightful articles on the latest trends and best practices in RTL design, and visit the tutorials section for step-by-step guides to mastering this critical aspect of hardware engineering. Connect with me to collaborate on innovative solutions and advance your knowledge in RTL design.
My Work Flow
- Operating System and Text Editor
- Folder Structure
- Design Scripts
Design Tools
Hardware
Important Concepts
- Throughput and Latency
- Synchronous and Asynchronous Reset
- Casex and Casez
- Full Case and Parallel Case
- Assign and If-Else Statement
- Blocking and Non-Blocking Assignment
- Always@(*) and Always_Comb
- Mealy Machine and Moore Machine
- Clock Gating
- Difference between “==” and “===”
Generic RTL Blocks
- Half Adder
- Full Adder
- Multiplexer
- De-Multiplexer
- Encoder
- Decoder
- Comparator
- Adder-Subtractor
- Register
- Shift Register
- Universal Shift Register
- Up/Down Counter
- Code Converter
- Mod-N Counter
- Ring Counter
- Edge Detector
- Frequency Divider
- Read Only Memory
FIFO Design
Static Timing Analysis
Clock Domain Crossing
- Theory
- Pulse Stretcher
- MUX Synchronization
- Two-Flop Synchronization
Communication Protocols
- UART
- SPI
- I2C
- VGA
- I2S
- HDMI
- AXI-Stream
- AXI4-Lite
- AXI-Interconnect
- 8b/10b Encoding
Pipeline
- Global stall
- Half-buffer
- Skid buffer
- 2-depth Fifo
- Pipeline Fifo
- Elastic Buffer
FPGA Projects
- Floating point unit
- AXI BUS interface
- DMA controller
- Error Correction Code
- DSP core for audio processing
- Phase-Locked Loop
- H.264 Video Encoder
- Convolution Neural Network
- Hardware Random Number generator
- Network-on-chip
- DDR Memory Controller
Computer Architecture
- Single Cycle MIPS Design
- Multi Cycle MIPS design
- RISC-V Core
FPGA as Accelerator
- 8-pt FFT Accelerator