R-Type

The R-type (register-type) instruction in RISC-V operates on three registers. Two of these registers serve as source registers rs2 and rs1, providing the input operands, while the third register rd functions as the destination register, storing the result of the operation. This format is commonly used for arithmetic and logical operations in the instruction set. Figure 1, illustrates the instruction format of the R-type instruction.

The R-Type instruction in RISC-V is a 32-bit instruction that contains essential information to execute arithmetic or logical operations. These 32 bits are divided into six different fields:

• Opcode: The opcode or operation code is a 7-bit field that defines the type of operation to be performed on the data stored in the source registers.
• Destination Register: Stores the result of the operation in the destination register rd.
• Function Fields: Together, these funct7 7-bit and 3-bit funct3 fields, known as control bits, determine the specific operation to be executed.
• Source Registers: Each, rs1 and rs2, 5-bit field holds the address of the input operands.

The table below provides a detailed breakdown of all R-Type instructions in RISC-V, along with their encoded information. For simplicity, the source (rs1, rs2) and destination (rd) registers are not included in the table but are used for describing the operations.