This directory explores the fundamentals of microarchitecture design, with the ultimate goal of developing a RISC-V core for FPGA implementation. Here, you’ll find insights into processor design, pipeline architecture, and the steps involved in bringing a custom RISC-V core to life on an FPGA.
Figure 1: RISC-V Instruction Set
Digital Design and Computer Architecture RISC-V Edition
My Workflow
Theory
Instruction Set
Single Cycle
- Microarchitecture Overview
- Data Path
- Control Path
- Design
- Trade-offs