I am currently a Graduate Research Assistant at Wright State University, where I am pursuing my Doctoral degree in Electrical Engineering. My research focuses on innovative solutions in digital design and signal processing. You can explore more about my research here.

During my internship at Ambarella, Inc., I gained hands-on experience in developing and automating timing assertions for MIPI-DPHY IP, optimizing the verification process for D-PHY data and clock lanes, and significantly reducing overall verification time. I also designed a three-phase encoding algorithm for MIPI-CPHY transmitter and receiver modules. My responsibilities involved performing formal verification by creating testbenches and assertions to ensure precise adherence to timing and functional specifications.

With a strong background in Digital Design, RTL Design, and FPGA Prototyping, I have also honed my skills as a Graduate Teaching Assistant while pursuing my Master’s Degree in Electrical Engineering. In this role, I guided students in modeling digital systems using hardware descriptive languages, implemented and tested their designs on FPGAs, and evaluated their performance through quizzes and grading in the Digital Integrated Circuit Design Lab.

Through these experiences, I have developed a deep passion for crafting efficient digital systems and mentoring others in the field of digital design and verification.

FPGAs are often compared to LEGO blocks where you can build a complex structure using small basic blocks. In my GitHub repositories I present to you some of these basic building blocks (basic designs in verilog/system verilog) that can be used as a foundation for building large and complex systems.